This invention relates to terminators which are applicable to metal oxide semiconductor on insulator (MOS-soi) with triple wells integrated circuit technology and which are particularly useful for terminator networks.
For signal interfaces between devices terminators have been used, as described for instance in U.S. Pat. No. 4,748,426: entitled xe2x80x9cActive termination circuit for computer interface usexe2x80x9d, granted May 31, 1988 to Alexander Stewart for Rodime PLC, in an active termination circuit for a computer interface for reducing line reflection of logic signals. Such terminators have used a first and second resistor combination to permanently connect to a signal line that couples a plurality of peripheral devices to one another. The other ends of the first and second resistors are connected through a switching device to a positive voltage supply line and to logic ground, respectively. When termination of multiple devices was required, a plurality of resistor combinations were provided but on/off control of the switch in this example was achieved by one control that is located remote from the termination circuit systems. Integrated circuit interconnection structures have also used precision terminating resistors, as illustrated by U.S. Pat. No. 4,228,369, granted in October, 1980 to Anantha et al. for IBM.
As will be illustrated for chip interconnection, when resistor terminators are used in thin film semiconductor integrated circuits such as those used in metal oxide semiconductors (e.g. CMOS) today, they create hot spots which cannot be adequately cooled, so such resistor terminator circuits which create hot spots cannot be used in metal oxide semiconductor applications to provide terminators for chip to chip connections on chips using IBM""s new sub-micron MOS (CMOS) technologies where because of the high currents used in these networks it is difficult or impossible to meet all the cooling and reliability requirements required for commercial performance. It has become necessary to invent a solution to interfacing devices which can be used in such environments on chips, and used for terminators in networks of chips and devices where there is a need to transmit digital data therebetween without overshoot and undershoot in signal transmission between the chips and devices or systems. These connections need to operate at a faster speed, accommodating data rate speeds ranging into hundreds of Mhz and Ghz.
The creation of a terminator which particularly may be fabricated for high speed metal oxide semiconductor on insulator (MOS-soi) applications with triple wells in integrated circuits is needed.
As a conventional CMOS receiver does not have good control on its threshold voltage to deal with small signals, the preferred embodiment provides a well balanced threshold voltage between the logic levels of a CMOS terminator circuit with an integrated receiver and implement hysteresis in its receiver, so that maximum noise tolerance between logic levels can be achieved for this network and digital system.
As the receiver is provided with hysteresis it can receive small signals properly and have enlarged noise tolerance between both logic levels.
This invention provides a terminator and receiver with hysteresis for the terminator network which is useful for fast transmission of digital data, eliminating or reducing overshoot and undershoot in signal transmission between chips and between systems, in serial links and data buses, for minimizing ringing and similar noise problems, for providing electrostatic discharge (ESD) protection, particularly in high speed metal oxide semiconductor (MOS) integrated circuit applications, and mixed vender technology interface communications. The demand for fast data transmission has pushed the data rate into hundreds of Mhz and Ghz and the preferred embodiment accommodates such speeds and reduces the signal swing so that the signal reach its desired digital ones or zeros voltage levels faster with lower power and with less noise generation.
The preferred embodiment of the invention control and adjustment of the impedance of the terminator so that it can operate the part in different packages as well as in system tuning for perfect termination. This will allow a part to have multiple usage""s. This provides a basis for cost saving on chips with part number reduction and a high volume ASIC OEM useful circuit.
The preferred embodiment of the invention control and adjustment of the center voltage of the terminator so that maximum signal can be received and it does not create skew between the zero and one logic levels In case of mixed signal interfaces.
These and other improvements are set forth in the following detailed description. For a better understanding of the invention with advantages and features, refer to the description and to the drawings.